Only 1 nanometer, the lowest power consumption! Peking University team achieves a significant breakthrough in chip technology

According to the official news from Peking University School of Electronics, Peking University has achieved a breakthrough in the field of non-volatile memory. The team led by Qiu Chenguang and Peng Lianmao from the School of Electronics successfully reduced the physical gate length of ferroelectric transistors to the 1-nanometer limit, creatively fabricating the smallest and lowest-power ferroelectric transistors to date. This development is expected to provide core device support for enhancing AI chip computing power and energy efficiency. The related research results were published online in the journal Science Advances.

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The Qiu Chenguang-Peng Lianmao team from the School of Electronics develops the world’s lowest power ferroelectric transistor

Peking University has made a groundbreaking advance in the field of non-volatile memory. The team from the School of Electronics first proposed the “Nano-gate ultra-low power ferroelectric transistor.” By precisely designing the device structure of ferroelectric memory and introducing the nano-gate electric field concentration enhancement effect, they developed a ferroelectric transistor that can operate at an ultra-low voltage of 0.6V, with energy consumption reduced to 0.45 fJ/μm, and the physical gate length shrunk to the 1-nanometer limit. This is the smallest and lowest-power ferroelectric transistor reported internationally so far, providing a new physical mechanism for constructing high-performance sub-1-nanometer node chips and high-computing-power AI chip architectures. This groundbreaking achievement is titled “Nanogate ferroelectric transistors with ultralow operation voltage of 0.6 V” and was published online in the journal Science Advances.

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Logic devices and memory devices are the two fundamental components for building integrated circuits. Logic units form the “computing and control center” of chips, while memory units serve as the “data warehouse.” Together, they account for over 70% of the integrated circuit market size. Driven by Moore’s Law, logic transistors have continuously improved performance through process miniaturization and architectural iteration. Currently, industry has achieved mass production of 2-nanometer node logic chips, and CMOS transistors operate at low voltages of 0.7V. In contrast, the performance development of non-volatile memory has lagged over decades; mainstream non-volatile Flash storage technology cannot be scaled down to advanced nodes, and most critically, Flash requires voltages above 5V for data erasure. As a result, existing chips must integrate step-up and step-down circuits between logic and non-volatile memory to convert working voltages, leading to additional area overhead and increased energy consumption. More importantly, the core of modern AI chip architecture lies in data flow optimization. Voltage mismatches between logic and memory directly cause data transfer issues, severely limiting AI chip computing power and significantly increasing energy consumption.

Outlook on voltage evolution of logic and memory chips and compatible nano-gate ferroelectric memory structures

Ferroelectric transistors utilize polarization reversal of ferroelectric materials for data storage, making them highly promising semiconductor memories in post-Moore chip technology, attracting widespread academic and industry attention. With their bistable polarization mechanism and three-terminal transistor structure, they are expected to enable non-volatile logic-in-memory architectures, achieving a perfect combination of storage and high-speed computation. This is a key new technology for breaking the “memory wall” and revolutionizing the underlying architecture of artificial intelligence. However, so far, limited by the physical constraints of flat ferroelectric coercive voltage, traditional ferroelectric transistors still require voltages above 1.5V to achieve polarization reversal and data erasure. Although better than Flash, conventional ferroelectric devices theoretically cannot reduce the voltage below 0.7V, making them incompatible with logic voltage levels. Achieving ultra-low voltage storage below 0.7V is critical for breaking through the storage wall bottleneck and enhancing AI chip computing power.

Electrical characterization of ultra-low voltage nano-gate ferroelectric transistors

In this work, the team led by Qiu Chenguang and Peng Lianmao first proposed the “nano-gate ferroelectric transistor structure” and the “nano-gate electric field enhancement mechanism.” By optimizing the device structure and cleverly shrinking the gate electrode to the nanoscale limit, they utilized the tip electric field concentration effect of the nano-gate to create highly localized strong electric field regions within the ferroelectric layer. This effectively amplified the local electric field strength, significantly lowering the ferroelectric polarization reversal voltage, surpassing the coercive voltage limits of conventional flat ferroelectric materials, and breaking the long-held notion that low voltage and high coercive electric fields are incompatible. They achieved an ultra-low operating voltage of 0.6V, reducing the ferroelectric storage voltage to a level comparable with logic voltages. The fabricated ferroelectric transistors have an energy consumption as low as 0.45 fJ/μm, an order of magnitude lower than existing international reports, with a storage speed approaching 1 nanosecond. This research is the first in the world to discover that ferroelectric transistors exhibit an anomalous size miniaturization advantage: when the physical gate length is shrunk to the extreme 1 nanometer, the electric field is significantly concentrated and enhanced, and the ultra-small gate size effectively improves ferroelectric storage characteristics, demonstrating that ferroelectric memory has significant advantages in constructing future sub-nanometer node chips.

Analysis of ultra-low power mechanisms in nano-gate ferroelectric transistors

(Source: Cailian News)